module i2s_transmit_top(
    input   wire    i_clk_50m,      //主时钟输入，连接至片上晶振（50MHz）
    input   wire    i_rst_n,        //复位信号输入
	//前级数据传入
	input   wire    [15:0]  i_i2s_txdata_l,     
    input   wire    [15:0]  i_i2s_txdata_r,     
	input	wire	i_i2s_txdata_vld,
    //i2s物理接口
    output  wire    o_i2s_sdata,    //串行数据输出
    output  wire    o_i2s_mclk,     //主时钟输出
    output  wire    o_i2s_bclk,     //bitclock输出
    output  wire    o_i2s_lrclk,    //lrclock输出
    //其他数据输出（连接至下一模块）
    output  wire    o_i2s_tx_ready	//可作为信号指示前级发送下一组信号
);

	//内部连线
	assign o_i2s_mclk = i_clk_50m;
	
	/*模块连接与整合*/
	//必要的端口总线定义
	wire	o_i2s_bclk_inst;
	assign	o_i2s_bclk = o_i2s_bclk_inst;
	
	wire	o_i2s_lrclk_inst;
	assign	o_i2s_lrclk = o_i2s_lrclk_inst;
	
	wire	i_rst_n_inst;
	assign	i_rst_n_inst = i_rst_n;
	//时钟产生模块
	//i2s_clk_gen模块
	i2s_clk_gen #(
		.BIT	(32)
	)ut_i2s_clk_gen(
    .clk_50m	(i_clk_50m),
    .rst_n		(i_rst_n_inst),
    .bclk		(o_i2s_bclk_inst),
    .lrclk		(o_i2s_lrclk_inst)
	);
	
	//i2s_transmitter 模块
	i2s_transmitter u_i2s_transmitter(
    .bclk		(o_i2s_bclk_inst),
    .lrclk		(o_i2s_lrclk_inst),
    .rst_n		(i_rst_n_inst),
	.data_vld	(i_i2s_txdata_vld),
	.rdata		(i_i2s_txdata_r),
	.ldata		(i_i2s_txdata_l),
	
	.ready		(o_i2s_tx_ready),
	.sdata		(o_i2s_sdata)
	);
	
endmodule
	
	